Hardware Transactional Memory (HTM) is a mechanism in computer architecture for supporting parallel programming. With HTM, programmers may simply declare a group of instructions as being part of a single speculative region and the HTM hardware may then guarantee that the instructions in the region are executed as a single atomic and isolated transaction. Atomicity means that all the instructions of the transaction are executed as a single atomic block with respect to all other concurrent threads of execution on one or more other processing cores in the system. Isolation means that no intermediate result of the transaction is exposed to the rest of the system until the transaction completes. HTM systems may allow transactions to run in parallel as long as they do not conflict. Two transactions may conflict when they both access the same memory area and either of the two transactions writes to that memory area.
To implement HTM, significant complexity must be added to processors and/or to memory subsystems. To deal with this complexity, processor architects have traditionally limited the feature set of a processor that implements HTM. For example, traditional HTM processors cannot utilize out-of-order execution optimizations while executing a speculative region of code. Out-of-order optimizations allow a processor to exploit instruction-level parallelism by executing instructions out of program order, temporarily storing the results of those instructions, and then writing the results to the memory hierarchy when all preceding instructions have done so. Since HTM processors do not use out-of-order execution to execute instruction sequences that are inside of speculative regions, traditional HTM processors may not execute instruction sequences in speculative regions as quickly as would otherwise be possible.